Accommodating workload diversity in chip multiprocessors via

09-Feb-2020 12:44 by 8 Comments

Accommodating workload diversity in chip multiprocessors via

Improving the performance of computer or other processing systems generally improves overall throughput and/or provides a better user experience.

We envision a diverse landscape of software in different stages of parallelization, from purely sequential, to fully parallel, to everything in between.Embodiments of the method of using the reconfigurable multiprocessor system of these teachings are also disclosed.For a better understanding of the present teachings, together with other and further needs thereof, reference is made to the accompanying drawings and detailed description and its scope will be pointed out in the appended claims. Google(); req('single_work'); $('.js-splash-single-step-signup-download-button').one('click', function(e){ req_and_ready('single_work', function() ); new c. A reconfigurable multiprocessor system including a number of processing units and components enabling executing sequential code collectively at processing units and enabling changing the architectural configuration of the processing units.Asymmetric chip multiprocessors (ACMPs) attempt to address this by providing cores with varying degrees of sophistication and computational capabilities.

The number and the complexity of cores are fixed at design time.Implementing multiprocessing (MP) systems, however, typically requires more than merely interconnecting processors in parallel.For example, tasks or programs may need to be divided so they can execute across parallel processing resources, memory consistency systems may be needed, etc.Hence, while ACMPs may deliver increased performance on sequential codes, they may do so at the expense of parallel performance, requiring a high level of software sophistication to maximize their potential.Instead of trying to find the right design trade-off between complex and simple cores (as ACMPs do), there is a need for a CMP that provides the flexibility to dynamically synthesize the right mix of simple and complex cores based on application requirements.a shows a graphical schematic block diagram of the exemplary embodiment.